Project: dsPIC33 ADC/DAC Loopback

Link to project

This piece of code is written for the dsPIC33FJ128GP802. It loops the audio from the ADC (AD0) to the right DAC channel. The purpose of this project is to have a DSP platform for digital audio effects and digital signal processing experiments (filters, etc).

The audio is sampled and output at a sample rate of 48000 samples/second. The ADC samples at 12 bit resolution and the DAC outputs 16 bit resolution.

The sampling is done using Direct Memory Access (DMA). This fills a buffer of 256 words with ADC samples. When the buffer is full, an interrupt occurs, switching to an other buffer. This makes it possible to do work on one of the buffers while the other one is being filled with new samples. For this project, however, samples are simply output without any other processing as shown in the figure below.

 

Flow chart of the ADC/DAC buffers in ping-pong mode.

The program is interrupt driven and the main function therefore does nothing. Serial interface is added for debugging purposes. It simply outputs UART data at 9600 baud, 8 bits + 1 stop bit, easily read by a UART-to-USB converter (an FTDI for example).

A Makefile is included in the project, making it possible to compile the program and flash the chip from the command line. More specifics on the Makefile is found here.

Below is shown a simplified schematic for getting audio in and out of the system. The input op amp biases the audio input to half the supply. The output differential amplifier makes the output single-ended. The op amps are MCP6002 rail-to-rail op amps.

A capacitor has been added to the input to filter out 48kHz spikes that were occuring when the ADC was sampling. The capacitor on the negative, differential output line is added to filter away out-of-band noise.

 

Simplified schematic for the project. The dsPIC33FJ128GP802 is hooked up/decoupled as specified in the datasheet. The analog reference is simply the 3.3V supply.

A photo of the mockup are shown below. The mockup is built on a copper clad board to improve high-speed performance.

 

Photo of the mockup.

The frequency response has been measured in the audio range (20–20,000Hz) and is shown below. The capacitors reduce the high frequency response just slightly but generally the response is quite flat.

 

Measured frequency response of the implementation. Here 0dB is the direct connection from input to output.